1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to various methods of forming metal silicide regions on an integrated circuit device, and to devices incorporating such metal silicide regions.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit elements in complex integrated circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits, wherein performance of the transistors in the speed critical signal paths substantially determines overall performance of the integrated circuit. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface positioned between highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
FIG. 1A schematically illustrates a cross-sectional view of an illustrative integrated circuit device 100 in an advanced manufacturing stage. As shown, the device 100 comprises a substrate 10, such as a semiconductor material and the like, that is divided into a plurality of active regions, which are to be understood as semiconductor regions, in and above which one or more transistors are to be formed. For example, one or more isolation regions 12, such as a shallow trench isolation, define and separate the substrate 10 into an illustrative PMOS region 10P, in and above which an illustrative PMOS transistor 100P will be formed, and an illustrative NMOS region 10N, in and above which an illustrative NMOS transistor 100N will be formed. Depending on the overall device requirements, the substrate 10 may be in bulk form (as depicted) or in the form of a silicon-on-insulator (SOI) construction comprised a of a bulk semiconductor layer, a buried insulating material and an active layer. At the point of fabrication depicted in FIG. 1A, each of the transistors includes an illustrative gate insulation layer 20, a illustrative gate electrode structure 24, source/drain regions 26, and sidewall spacers 28 (on the PMOS device 100P) and 30 (on the NMOS device 100N). Each of these components may be formed using a variety of known materials and techniques. The gate insulation layer 20 and the gate electrode structure 24 are intended to be schematic and representative in nature in that they may be comprised on a variety of different materials and the may not be the same for each of the PMOS device 100P and the NMOS device 100N. For example, the NMOS device 100N may have gate insulation layer 20 made of silicon dioxide and a gate electrode 24 made of polysilicon, while the PMOS device 100P may have a gate insulation layer 20 that includes a high-k dielectric material (k value greater than 10). The illustrative source/drain regions 26 are formed by performing the appropriate ion implantation process such that, after performing a heat treatment process, the source/drain regions 26 have the appropriate lateral and vertical dopant profile so as to comply with the requirements of the devices 100P, 100N. The illustrative spacers 28, 30 may be initially formed by depositing a layer of spacer material, e.g., an insulator such as silicon nitride, silicon dioxide, etc., and thereafter performing an anisotropic etching process. The spacers 28 and/or 30 may be formed directly on the sidewalls of the gate electrode 24, or there may be liner or other spacer positioned between the spacers 28, 30 and its associated gate electrode 24.
After the spacers 28, 30 are initially formed, the PMOS device 100P and the NMOS device 100N are typically subjected to differing process operations in part because of the different materials of construction and structure of the two different devices. For example, in one illustrative example, the PMOS device 100P may include an epitaxial layer of silicon germanium that is formed in the substrate 10 at least under the gate insulation layer 20. Additionally, in some cases, the PMOS device 100P has one or more layer of silicon germanium formed in the substrate 10 in the area where the source/drain region 26 will be formed for the PMOS device 100P. These structures are typically formed to enhance the performance of the PMOS device 100P, and they are typically not formed on the NMOS device 100N. Among other things, such difference mean that the PMOS device 100P may be subject to different and perhaps more processing operations than the NMOS device 100N, such as additional etching processes. As a result of such different processing, the height of the spacers 28 on the PMOS device 100P is less than the height of the spacers 30 on the NMOS device 100N. Stated another way, there is more spacer “pull-back” on the PMOS transistor 100P than on the NMOS transistor 100N.
The next step in the manufacture of the devices 100P, 100N involves the formation of metal silicide regions, e.g., nickel-platinum metal silicide regions, on the source/drain regions 26 and on the gate electrodes 24. Such metal silicide regions may be formed using a variety of materials and using a variety of know techniques. As shown in FIG. 1B, a layer of a refractory metal 32, e.g., nickel, platinum, cobalt, etc., or combinations thereof, is blanket-deposited on the device 100. Thereafter, as shown in FIG. 1C, one or more heating processes are performed to convert the portions of the layer of refractory metal 32 that are in contact with a silicon-containing material, like the gate electrode 24 and the source/drain regions 26, to metal silicide regions 34 (on the source/drain regions 26) and metal silicide regions 36P, 36N on the PMOS device 100P and the NMOS device 100N, respectively.
There are several potential problems with the aforementioned processing scheme. First, in modern semiconductor devices, the space between the gate electrode for the PMOS device 100P and the gate electrode 24 for the NMOS device 100N is very small, e.g., on the order of approximately 60-90 nm. As a result, the thickness of the layer of refractory metal 32 that is actually deposited on the substrate 10 between the gate electrode structures 24 is relatively thin, e.g., 5-15 nm, as compared to the thickness of the layer of refractory metal 32 that is deposited above the gate electrodes 24 which may be about 10-25 nm in thickness, because the step coverage during the deposition of the layer of refractory metal 32 is aspect ratio dependent. As a result, the thickness of the metal silicide regions 34 on the source/drain regions 26 may tend to be much thinner than the metal silicide regions 36P, 36N. Additionally, the lateral position of the metal silicide regions 36 relative to the channel regions of the devices 100P, 100N tends to be defined by the base thickness of the spacers 28, 30, which may not be the same for both of the devices 100P, 100N. In some cases, the metal silicide regions 36 may be made of a metal silicide, e.g., nickel silicide, that tends to grow aggressively under the edge of the spacers 28, 30 toward the channel region of the respective devices. If the metal silicide regions 34 creep to far toward the channel region, the resulting device may exhibit greater leakage currents that anticipated or desired, which may adversely impact the performance of the resulting transistor devices. Both of the metal silicide regions 36P, 36N typically tend to exhibit a mushroom-type configuration because of the spacer “pull-back” on both of the devices 100P, 100N. However, due to the greater spacer “pull-back” on the PMOS device 100P, the metal silicide region 36P on the PMOS device 100P tends to be larger than the metal silicide region 36N on the NMOS device 100N. This size difference occurs because of the exposure of the additional surface area of the gate electrode 24 for the PMOS device 100P. Such size differences can be problematic in modern semiconductor devices which very small spacing between adjacent gate electrode structures 24. Moreover, depending upon the size of the metal silicide regions 36P, 36N, and there position, i.e., they may not be positioned directly over the gate electrodes 24 as depicted, it may be difficult to form a contact to the source/drain region 26 without shorting-out to at least one of the metal silicide regions 36P, 36N.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.